No Cost Qualification !!!
MICRO RECLAIM TECHNOLOGIES LLC SILICON CARBIDE & GALLIUM NITRIDE RECLAIM
PROVIDING STATE OF THE ART RE-POLISHING SERVICES OF HIGH PERFORMANCE SEMICONDUCTOR WAFERS FOR EPITAXY RE-GROWTH
No Cost Qualification !!!
PROVIDING STATE OF THE ART RE-POLISHING SERVICES OF HIGH PERFORMANCE SEMICONDUCTOR WAFERS FOR EPITAXY RE-GROWTH
Power semiconductors are ideal for applications such as on-board chargers and inverters used within plug-in hybrid and fully electric vehicles .
SiC and GaN offer many advantages in RF power and power-switching applications that require high voltage, high power density, and operation at high temperatures.
Power electronics are used in conversion units in wind generation systems .
Established in July of 2014, our facility is conveniently located in Fort Lauderdale Florida.
MRT was modeled and built to handle high capacity wafer re-polishing by utilizing an efficient process flow and strategic placement of all our process and test equipment. We've developed a Quality Management System to ensure all work is performed diligently and accurately. Realizing every wafer re-polish job is different, and each has its unique challenges, our 25 plus years of experience in the Compound Semiconductor Industry is so broad, we are equipped to handle any challenge that could possibly occur.
In Semiconductor manufacturing , the substrate has the highest expense of all materials used. Due to the high cost of Silicon Carbide Wafers , reclaiming is the most cost effective way to maximize its value and reducing scrap costs.
At MRT, we focus on understanding customer's needs by communication, planning, organizing, and having the knowledge base and dedication to conduct business in an honest and ethical manner. This includes product and IP confidentiality.
Our track record is just as impressive. We currently service companies who are the largest users of SiC wafers in the world. Customers, whose trust we've earned with quality work and the highest levels of professionalism.
Give us an opportunity to provide this re-polish service to you. You'll be glad you did.
Recognizing the value of your non-conforming wafer by reclaiming will reduce your yield losses. Reclaimed wafers provide its greatest value when used in epi-reactor calibrations performed after maintenance events , source changes , and regular process monitoring. The same wafer can be cycled through multiple times, further reducing these costs.
MRT is committed to understand, meet and, when possible, exceed our Customer's Requirements through the continuous improvement of our processes. We are dedicated to performing reclaim services at the best quality and most competitive cost possible.
MRT has worked closely with substrate manufacturers to develop an effective process yielding high quality , low Si-Face roughness ,epi-ready substrates. We offer epi removal, and re-polishing services on Semi-Insulating and N-Type Silicon Carbide wafers ranging in diameters from 2in, 3 in, 4in and 6in. We reclaim both 6H and 4H poly-types with either on-axis or off-axis surface orientations. MRT also offers re-polishing services on GaN ,and Sapphire wafers yielding an equally high quality surface finish.
Polish and CMP reclaim processes yielding a low roughness ( Sa < 5A ) , epi-ready , scratch free surface , enabling epitaxial re-growth , thus reducing costs associated with yield loss.
2" , 3" , 4" and 6" Diameter wafers
GaN, AlGaN, AlN, and SiC epi removal and surface preparation for epi ready wafer
Removal of metalization and and nitrides , remaining epitaxy , CMP
Removal of epaitaxy , CMP
"Kiss" polish removal of residual material from back of Epitaxial Wafer with no damage to Epi Structure
Defects on the backside of a wafer during epi growth can come from many sources. Residuals and scratches can be caused by handling equipment , robots and chucks , and also transferred from wafer carrier pockets . Backside defects can cause areas of poor lithography patterns on the front side of the wafer resulting in yield loss. We have worked with our customers to develop a non aggressive polishing process which not only removes the defect , but also does not affect the SBIR of the wafer , which is a very important parameter in small die fabrication.
MRT provides state of the art wafer
wafer thinning services to manufacturers of semiconductor devices. Thinning is required for stacking and high-density I.C. packaging . Keeping the wafer uniformity is highly critical during this process. By utilizing our polishing technology ,final results yield thicknesses down to 50 um and TTV =/< 5um for 100mm Wafer.
Specialized cleaning for removal of residual Mercury ( Hg ) when performing Capacitance ( Cv ) testing on your Epi Wafers. Recover post epi fallout by sending us your high particle count failures.
cleaning process yielding an ultra-clean , damage free surface area performed in a clean room environment.
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Surface Analysis including roughness (Sa) and 3D profiling
measurement data using a contactless system. Data includes- Average Wafer Thickness, TTV, TIR, Bow , Warp
packaged and labeled per customers requirements
1500 W. Cypress Creek Rd. STE 514 , Fort Lauderdale, Florida 33309, United States
Open today | 09:00 am – 05:00 pm |
Monday - Friday: 9am - 5pm
Saturday: By appointment
Sunday: Closed
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